The lib-micro C API Reference

C Structs

struct u_result_t

C Functions

Functions

u64 ldat_array_read(u64 pdat_reg, u64 array_sel, u64 bank_sel, u64 dword_idx, u64 fast_addr)

Read a single value dircetly from LDAT.

Parameters:

pdat_reg – Register index selecting specific device for LDAT to inspect.
array_sel – Array index to read from.
bank_sel – Bank selector.
dword_idx – Double word index within the specified bank.
fast_addr – Address to read from.

Returns:

The vaule reading from LDAT.

void ldat_array_write(u64 pdat_reg, u64 array_sel, u64 bank_sel, u64 dword_idx, u64 fast_addr, u64 val)

Write a single value dircetly to LDAT.

Parameters:

pdat_reg – Register index selecting specific device for LDAT to inspect.
array_sel – Array index to read from.
bank_sel – Bank selector.
dword_idx – Double word index within the specified bank.
fast_addr – Address to read from.
val – Value to write.

void ms_array_write(u64 array_sel, u64 bank_sel, u64 dword_idx, u64 fast_addr, u64 val)

Write a single value from a microsequencer array.

Parameters:

array_sel – The array index to read.
bank_sel – Should be 0 for all ms array read/write operations as only a single bank exists.
dword_idx – Should be 0 for same reasons as bank_sel.
fast_addr – the address to write to.
val – The vaule to write.

u64 ms_array_read(u64 array_sel, u64 bank_sel, u64 dword_idx, u64 fast_addr)

Read a single value from a microsequencer array.

Parameters:

array_sel – The array index to read.
bank_sel – Should be 0 for all ms array read/write operations as only a single bank exists.
dword_idx – Should be 0 for same reasons as bank_sel.
fast_addr – The address to read from.

Returns:

A value read from the specified ms_array index and address.

static u64 ms_array_0_read(u64 addr)

Read a single value from ms_array 0.

This function is a wrapper around ms_array_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

static u64 ms_array_1_read(u64 addr)

Read a single value from ms_array 1.

This function is a wrapper around ms_array_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

static u64 ms_array_2_read(u64 addr)

Read a single value from ms_array 2.

This function is a wrapper around ms_array_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

static u64 ms_array_3_read(u64 addr)

Read a single value from ms_array 3.

This function is a wrapper around ms_array_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

static u64 ms_array_4_read(u64 addr)

Read a single value from ms_array 4.

This function is a wrapper around ms_array_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

u64 ms_ro_code_read(u64 addr)

Read a single microcode instruction from read only address space.

This function is a simple alias for ms_array_0_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

u64 ms_ro_seq_read(u64 addr)

Read a single sequence word from read only address space.

This function is a simple alias for ms_array_1_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

u64 ms_rw_seq_read(u64 addr)

Read a single sequence word from read/write address space.

This function is a simple alias for ms_array_2_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

u64 ms_match_n_patch_read(u64 addr)

Read a single sequence word from match and patch.

This function is a simple alias for ms_array_3_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

u64 ms_rw_code_read(u64 addr)

Read a single microcode instruction from read/write address space.

This function is a simple alias for ms_array_4_read.

Parameters:: addr – The address to read from.
Returns:: The vaule read from microsequencer.

static void ms_array_2_write(u64 addr, u64 val)

write a single microcode instruction to ms_array 2.

Parameters:

addr – The address to write to.
val – microcode instruction to write as a uint64_t.

static void ms_array_3_write(u64 addr, u64 val)

write a single microcode instruction to ms_array 3.

Parameters:

addr – The address to write to.
val – microcode instruction to write as a uint64_t.

static void ms_array_4_write(u64 addr, u64 val)

write a single microcode instruction to ms_array 4.

Parameters:

addr – The address to write to.
val – microcode instruction to write as a uint64_t.

void ms_rw_seq_write(u64 addr, u64 val)

write a single sequence word to the read/write address space.

This function is a simple alias for ms_array_2_write.

Parameters:

addr – The address to write to.
val – microcode instruction to write as a uint64_t.

void ms_match_n_patch_write(u64 addr, u64 val)

write a single entry to match and patch.

This function is a simple alias for ms_array_3_write.

Parameters:

addr – The address to write to.
val – microcode instruction to write as a uint64_t.

void ms_rw_code_write(u64 addr, u64 val)

write a single microcode instruction to the read/write address space.

This function is a simple alias for ms_array_4_write.

Parameters:

addr – The address to write to.
val – microcode instruction to write as a uint64_t.

static inline void enable_match_and_patch(void): enable match and pach which esetialy enables microcode updates.

static inline void disable_match_and_patch(void): disable match and pach which esetialy disables microcode updates.

uCode macros

group UJMP

Defines

UJMP_I(imm)

UJMP_R(src)

group MOVE

Defines

MOVE_DSZ8_DR(dst, src)

MOVE_DSZ8_DI(dst, imm)

MOVE_DSZ8_DM(dst, macro)

MOVE_DSZ16_DR(dst, src)

MOVE_DSZ16_DI(dst, imm)

MOVE_DSZ16_DM(dst, macro)

MOVE_DSZ32_DR(dst, src)

MOVE_DSZ32_DI(dst, imm)

MOVE_DSZ32_DM(dst, macro)

MOVE_DSZ64_DR(dst, src)

MOVE_DSZ64_DI(dst, imm)

MOVE_DSZ64_DM(dst, macro)

group ZEROEXT

Defines

ZEROEXT_DSZ8_DR(dst, src)

ZEROEXT_DSZ8_DI(dst, imm)

ZEROEXT_DSZ8_DM(dst, macro)

ZEROEXT_DSZ16_DR(dst, src)

ZEROEXT_DSZ16_DI(dst, imm)

ZEROEXT_DSZ16_DM(dst, macro)

ZEROEXT_DSZ32_DR(dst, src)

ZEROEXT_DSZ32_DI(dst, imm)

ZEROEXT_DSZ32_DM(dst, macro)

ZEROEXT_DSZ64_DR(dst, src)

ZEROEXT_DSZ64_DI(dst, imm)

ZEROEXT_DSZ64_DM(dst, macro)

group MOVETOCREG

Defines

MOVETOCREG_DSZ8_RI(src, imm)

MOVETOCREG_DSZ8_RR(src0, src1)

MOVETOCREG_DSZ16_RI(src, imm)

MOVETOCREG_DSZ16_RR(src0, src1)

MOVETOCREG_DSZ32_RI(src, imm)

MOVETOCREG_DSZ32_RR(src0, src1)

MOVETOCREG_DSZ64_RI(src, imm)

MOVETOCREG_DSZ64_RR(src0, src1)

group MOVEFROMCREG

Defines

MOVEFROMCREG_DSZ8_DI(dst, imm)

MOVEFROMCREG_DSZ8_DR(dst, src)

MOVEFROMCREG_DSZ16_DI(dst, imm)

MOVEFROMCREG_DSZ16_DR(dst, src)

MOVEFROMCREG_DSZ32_DI(dst, imm)

MOVEFROMCREG_DSZ32_DR(dst, src)

MOVEFROMCREG_DSZ64_DI(dst, imm)

MOVEFROMCREG_DSZ64_DR(dst, src)

group WRITEURAM

Defines

WRITEURAM_RI(src, imm)

WRITEURAM_RR(src0, src1)

group READURAM

Defines

READURAM_DI(dst, imm)

READURAM_DR(dst, src)

group MSR2CR

Defines

MSR2CR_DR(dst, src)

MSR2CR_DI(dst, imm)

group WRMSLOOPCTRFBR

Defines

WRMSLOOPCTRFBR_R(src)

WRMSLOOPCTRFBR_I(imm)

group GENARITHFLAGS

Defines

GENARITHFLAGS_R(src)

GENARITHFLAGS_RR(src0, src1)

GENARITHFLAGS_IR(imm, src)

group SIGEVENT

Defines

SIGEVENT_I(imm)

SIGEVENT_RI(src, imm)

SIGEVENT_DI(dst, imm)

SIGEVENT_DRI(dst, src, imm)

SIGEVENT_IR(imm, src)

SIGEVENT_DIR(dst, imm, src)

group READAFLAGS

Defines

READAFLAGS_DR(dst, src)

group FPREADROM_DTYPENOP

Defines

FPREADROM_DTYPENOP_DR(dst, src)

group ADD

Defines

ADD_DSZ8_DRI(dst, src, imm)

ADD_DSZ8_DIR(dst, imm, src)

ADD_DSZ8_DRM(dst, src, macro)

ADD_DSZ8_DMR(dst, macro, src)

ADD_DSZ8_DRR(dst, src0, src1)

ADD_DSZ16_DRI(dst, src, imm)

ADD_DSZ16_DIR(dst, imm, src)

ADD_DSZ16_DRM(dst, src, macro)

ADD_DSZ16_DMR(dst, macro, src)

ADD_DSZ16_DRR(dst, src0, src1)

ADD_DSZ32_DRI(dst, src, imm)

ADD_DSZ32_DIR(dst, imm, src)

ADD_DSZ32_DRM(dst, src, macro)

ADD_DSZ32_DMR(dst, macro, src)

ADD_DSZ32_DRR(dst, src0, src1)

ADD_DSZ64_DRI(dst, src, imm)

ADD_DSZ64_DIR(dst, imm, src)

ADD_DSZ64_DRM(dst, src, macro)

ADD_DSZ64_DMR(dst, macro, src)

ADD_DSZ64_DRR(dst, src0, src1)

group OR

Defines

OR_DSZ8_DRI(dst, src, imm)

OR_DSZ8_DIR(dst, imm, src)

OR_DSZ8_DRM(dst, src, macro)

OR_DSZ8_DMR(dst, macro, src)

OR_DSZ8_DRR(dst, src0, src1)

OR_DSZ16_DRI(dst, src, imm)

OR_DSZ16_DIR(dst, imm, src)

OR_DSZ16_DRM(dst, src, macro)

OR_DSZ16_DMR(dst, macro, src)

OR_DSZ16_DRR(dst, src0, src1)

OR_DSZ32_DRI(dst, src, imm)

OR_DSZ32_DIR(dst, imm, src)

OR_DSZ32_DRM(dst, src, macro)

OR_DSZ32_DMR(dst, macro, src)

OR_DSZ32_DRR(dst, src0, src1)

OR_DSZ64_DRI(dst, src, imm)

OR_DSZ64_DIR(dst, imm, src)

OR_DSZ64_DRM(dst, src, macro)

OR_DSZ64_DMR(dst, macro, src)

OR_DSZ64_DRR(dst, src0, src1)

group AND

Defines

AND_DSZ8_DRI(dst, src, imm)

AND_DSZ8_DIR(dst, imm, src)

AND_DSZ8_DRM(dst, src, macro)

AND_DSZ8_DMR(dst, macro, src)

AND_DSZ8_DRR(dst, src0, src1)

AND_DSZ16_DRI(dst, src, imm)

AND_DSZ16_DIR(dst, imm, src)

AND_DSZ16_DRM(dst, src, macro)

AND_DSZ16_DMR(dst, macro, src)

AND_DSZ16_DRR(dst, src0, src1)

AND_DSZ32_DRI(dst, src, imm)

AND_DSZ32_DIR(dst, imm, src)

AND_DSZ32_DRM(dst, src, macro)

AND_DSZ32_DMR(dst, macro, src)

AND_DSZ32_DRR(dst, src0, src1)

AND_DSZ64_DRI(dst, src, imm)

AND_DSZ64_DIR(dst, imm, src)

AND_DSZ64_DRM(dst, src, macro)

AND_DSZ64_DMR(dst, macro, src)

AND_DSZ64_DRR(dst, src0, src1)

group SUB

Defines

SUB_DSZ8_DRI(dst, src, imm)

SUB_DSZ8_DIR(dst, imm, src)

SUB_DSZ8_DRM(dst, src, macro)

SUB_DSZ8_DMR(dst, macro, src)

SUB_DSZ8_DRR(dst, src0, src1)

SUB_DSZ16_DRI(dst, src, imm)

SUB_DSZ16_DIR(dst, imm, src)

SUB_DSZ16_DRM(dst, src, macro)

SUB_DSZ16_DMR(dst, macro, src)

SUB_DSZ16_DRR(dst, src0, src1)

SUB_DSZ32_DRI(dst, src, imm)

SUB_DSZ32_DIR(dst, imm, src)

SUB_DSZ32_DRM(dst, src, macro)

SUB_DSZ32_DMR(dst, macro, src)

SUB_DSZ32_DRR(dst, src0, src1)

SUB_DSZ64_DRI(dst, src, imm)

SUB_DSZ64_DIR(dst, imm, src)

SUB_DSZ64_DRM(dst, src, macro)

SUB_DSZ64_DMR(dst, macro, src)

SUB_DSZ64_DRR(dst, src0, src1)

group SUBR

Defines

SUBR_DSZ8_DRI(dst, src, imm)

SUBR_DSZ8_DIR(dst, imm, src)

SUBR_DSZ8_DRM(dst, src, macro)

SUBR_DSZ8_DMR(dst, macro, src)

SUBR_DSZ8_DRR(dst, src0, src1)

SUBR_DSZ16_DRI(dst, src, imm)

SUBR_DSZ16_DIR(dst, imm, src)

SUBR_DSZ16_DRM(dst, src, macro)

SUBR_DSZ16_DMR(dst, macro, src)

SUBR_DSZ16_DRR(dst, src0, src1)

SUBR_DSZ32_DRI(dst, src, imm)

SUBR_DSZ32_DIR(dst, imm, src)

SUBR_DSZ32_DRM(dst, src, macro)

SUBR_DSZ32_DMR(dst, macro, src)

SUBR_DSZ32_DRR(dst, src0, src1)

SUBR_DSZ64_DRI(dst, src, imm)

SUBR_DSZ64_DIR(dst, imm, src)

SUBR_DSZ64_DRM(dst, src, macro)

SUBR_DSZ64_DMR(dst, macro, src)

SUBR_DSZ64_DRR(dst, src0, src1)

group XOR

Defines

XOR_DSZ8_DRI(dst, src, imm)

XOR_DSZ8_DIR(dst, imm, src)

XOR_DSZ8_DRM(dst, src, macro)

XOR_DSZ8_DMR(dst, macro, src)

XOR_DSZ8_DRR(dst, src0, src1)

XOR_DSZ16_DRI(dst, src, imm)

XOR_DSZ16_DIR(dst, imm, src)

XOR_DSZ16_DRM(dst, src, macro)

XOR_DSZ16_DMR(dst, macro, src)

XOR_DSZ16_DRR(dst, src0, src1)

XOR_DSZ32_DRI(dst, src, imm)

XOR_DSZ32_DIR(dst, imm, src)

XOR_DSZ32_DRM(dst, src, macro)

XOR_DSZ32_DMR(dst, macro, src)

XOR_DSZ32_DRR(dst, src0, src1)

XOR_DSZ64_DRI(dst, src, imm)

XOR_DSZ64_DIR(dst, imm, src)

XOR_DSZ64_DRM(dst, src, macro)

XOR_DSZ64_DMR(dst, macro, src)

XOR_DSZ64_DRR(dst, src0, src1)

group NOTAND

Defines

NOTAND_DSZ8_DRI(dst, src, imm)

NOTAND_DSZ8_DIR(dst, imm, src)

NOTAND_DSZ8_DRM(dst, src, macro)

NOTAND_DSZ8_DMR(dst, macro, src)

NOTAND_DSZ8_DRR(dst, src0, src1)

NOTAND_DSZ16_DRI(dst, src, imm)

NOTAND_DSZ16_DIR(dst, imm, src)

NOTAND_DSZ16_DRM(dst, src, macro)

NOTAND_DSZ16_DMR(dst, macro, src)

NOTAND_DSZ16_DRR(dst, src0, src1)

NOTAND_DSZ32_DRI(dst, src, imm)

NOTAND_DSZ32_DIR(dst, imm, src)

NOTAND_DSZ32_DRM(dst, src, macro)

NOTAND_DSZ32_DMR(dst, macro, src)

NOTAND_DSZ32_DRR(dst, src0, src1)

NOTAND_DSZ64_DRI(dst, src, imm)

NOTAND_DSZ64_DIR(dst, imm, src)

NOTAND_DSZ64_DRM(dst, src, macro)

NOTAND_DSZ64_DMR(dst, macro, src)

NOTAND_DSZ64_DRR(dst, src0, src1)

group ROL

Defines

ROL_DSZ8_DRI(dst, src, imm)

ROL_DSZ8_DIR(dst, imm, src)

ROL_DSZ8_DRM(dst, src, macro)

ROL_DSZ8_DMR(dst, macro, src)

ROL_DSZ8_DRR(dst, src0, src1)

ROL_DSZ16_DRI(dst, src, imm)

ROL_DSZ16_DIR(dst, imm, src)

ROL_DSZ16_DRM(dst, src, macro)

ROL_DSZ16_DMR(dst, macro, src)

ROL_DSZ16_DRR(dst, src0, src1)

ROL_DSZ32_DRI(dst, src, imm)

ROL_DSZ32_DIR(dst, imm, src)

ROL_DSZ32_DRM(dst, src, macro)

ROL_DSZ32_DMR(dst, macro, src)

ROL_DSZ32_DRR(dst, src0, src1)

ROL_DSZ64_DRI(dst, src, imm)

ROL_DSZ64_DIR(dst, imm, src)

ROL_DSZ64_DRM(dst, src, macro)

ROL_DSZ64_DMR(dst, macro, src)

ROL_DSZ64_DRR(dst, src0, src1)

group ROR

Defines

ROR_DSZ8_DRI(dst, src, imm)

ROR_DSZ8_DIR(dst, imm, src)

ROR_DSZ8_DRM(dst, src, macro)

ROR_DSZ8_DMR(dst, macro, src)

ROR_DSZ8_DRR(dst, src0, src1)

ROR_DSZ16_DRI(dst, src, imm)

ROR_DSZ16_DIR(dst, imm, src)

ROR_DSZ16_DRM(dst, src, macro)

ROR_DSZ16_DMR(dst, macro, src)

ROR_DSZ16_DRR(dst, src0, src1)

ROR_DSZ32_DRI(dst, src, imm)

ROR_DSZ32_DIR(dst, imm, src)

ROR_DSZ32_DRM(dst, src, macro)

ROR_DSZ32_DMR(dst, macro, src)

ROR_DSZ32_DRR(dst, src0, src1)

ROR_DSZ64_DRI(dst, src, imm)

ROR_DSZ64_DIR(dst, imm, src)

ROR_DSZ64_DRM(dst, src, macro)

ROR_DSZ64_DMR(dst, macro, src)

ROR_DSZ64_DRR(dst, src0, src1)

group RAS

Defines

RAS_DSZ8_DRI(dst, src, imm)

RAS_DSZ8_DIR(dst, imm, src)

RAS_DSZ8_DRM(dst, src, macro)

RAS_DSZ8_DMR(dst, macro, src)

RAS_DSZ8_DRR(dst, src0, src1)

RAS_DSZ16_DRI(dst, src, imm)

RAS_DSZ16_DIR(dst, imm, src)

RAS_DSZ16_DRM(dst, src, macro)

RAS_DSZ16_DMR(dst, macro, src)

RAS_DSZ16_DRR(dst, src0, src1)

RAS_DSZ32_DRI(dst, src, imm)

RAS_DSZ32_DIR(dst, imm, src)

RAS_DSZ32_DRM(dst, src, macro)

RAS_DSZ32_DMR(dst, macro, src)

RAS_DSZ32_DRR(dst, src0, src1)

RAS_DSZ64_DRI(dst, src, imm)

RAS_DSZ64_DIR(dst, imm, src)

RAS_DSZ64_DRM(dst, src, macro)

RAS_DSZ64_DMR(dst, macro, src)

RAS_DSZ64_DRR(dst, src0, src1)

group SHL

Defines

SHL_DSZ8_DRI(dst, src, imm)

SHL_DSZ8_DIR(dst, imm, src)

SHL_DSZ8_DRM(dst, src, macro)

SHL_DSZ8_DMR(dst, macro, src)

SHL_DSZ8_DRR(dst, src0, src1)

SHL_DSZ16_DRI(dst, src, imm)

SHL_DSZ16_DIR(dst, imm, src)

SHL_DSZ16_DRM(dst, src, macro)

SHL_DSZ16_DMR(dst, macro, src)

SHL_DSZ16_DRR(dst, src0, src1)

SHL_DSZ32_DRI(dst, src, imm)

SHL_DSZ32_DIR(dst, imm, src)

SHL_DSZ32_DRM(dst, src, macro)

SHL_DSZ32_DMR(dst, macro, src)

SHL_DSZ32_DRR(dst, src0, src1)

SHL_DSZ64_DRI(dst, src, imm)

SHL_DSZ64_DIR(dst, imm, src)

SHL_DSZ64_DRM(dst, src, macro)

SHL_DSZ64_DMR(dst, macro, src)

SHL_DSZ64_DRR(dst, src0, src1)

group SHR

Defines

SHR_DSZ8_DRI(dst, src, imm)

SHR_DSZ8_DIR(dst, imm, src)

SHR_DSZ8_DRM(dst, src, macro)

SHR_DSZ8_DMR(dst, macro, src)

SHR_DSZ8_DRR(dst, src0, src1)

SHR_DSZ16_DRI(dst, src, imm)

SHR_DSZ16_DIR(dst, imm, src)

SHR_DSZ16_DRM(dst, src, macro)

SHR_DSZ16_DMR(dst, macro, src)

SHR_DSZ16_DRR(dst, src0, src1)

SHR_DSZ32_DRI(dst, src, imm)

SHR_DSZ32_DIR(dst, imm, src)

SHR_DSZ32_DRM(dst, src, macro)

SHR_DSZ32_DMR(dst, macro, src)

SHR_DSZ32_DRR(dst, src0, src1)

SHR_DSZ64_DRI(dst, src, imm)

SHR_DSZ64_DIR(dst, imm, src)

SHR_DSZ64_DRM(dst, src, macro)

SHR_DSZ64_DMR(dst, macro, src)

SHR_DSZ64_DRR(dst, src0, src1)

group CONCAT

Defines

CONCAT_DSZ8_DRI(dst, src, imm)

CONCAT_DSZ8_DIR(dst, imm, src)

CONCAT_DSZ8_DRM(dst, src, macro)

CONCAT_DSZ8_DMR(dst, macro, src)

CONCAT_DSZ8_DRR(dst, src0, src1)

CONCAT_DSZ16_DRI(dst, src, imm)

CONCAT_DSZ16_DIR(dst, imm, src)

CONCAT_DSZ16_DRM(dst, src, macro)

CONCAT_DSZ16_DMR(dst, macro, src)

CONCAT_DSZ16_DRR(dst, src0, src1)

CONCAT_DSZ32_DRI(dst, src, imm)

CONCAT_DSZ32_DIR(dst, imm, src)

CONCAT_DSZ32_DRM(dst, src, macro)

CONCAT_DSZ32_DMR(dst, macro, src)

CONCAT_DSZ32_DRR(dst, src0, src1)

CONCAT_DSZ64_DRI(dst, src, imm)

CONCAT_DSZ64_DIR(dst, imm, src)

CONCAT_DSZ64_DRM(dst, src, macro)

CONCAT_DSZ64_DMR(dst, macro, src)

CONCAT_DSZ64_DRR(dst, src0, src1)

group MOVEINSERTFLGS

Defines

MOVEINSERTFLGS_DSZ8_DRI(dst, src, imm)

MOVEINSERTFLGS_DSZ8_DIR(dst, imm, src)

MOVEINSERTFLGS_DSZ8_DRM(dst, src, macro)

MOVEINSERTFLGS_DSZ8_DMR(dst, macro, src)

MOVEINSERTFLGS_DSZ8_DRR(dst, src0, src1)

MOVEINSERTFLGS_DSZ16_DRI(dst, src, imm)

MOVEINSERTFLGS_DSZ16_DIR(dst, imm, src)

MOVEINSERTFLGS_DSZ16_DRM(dst, src, macro)

MOVEINSERTFLGS_DSZ16_DMR(dst, macro, src)

MOVEINSERTFLGS_DSZ16_DRR(dst, src0, src1)

MOVEINSERTFLGS_DSZ32_DRI(dst, src, imm)

MOVEINSERTFLGS_DSZ32_DIR(dst, imm, src)

MOVEINSERTFLGS_DSZ32_DRM(dst, src, macro)

MOVEINSERTFLGS_DSZ32_DMR(dst, macro, src)

MOVEINSERTFLGS_DSZ32_DRR(dst, src0, src1)

MOVEINSERTFLGS_DSZ64_DRI(dst, src, imm)

MOVEINSERTFLGS_DSZ64_DIR(dst, imm, src)

MOVEINSERTFLGS_DSZ64_DRM(dst, src, macro)

MOVEINSERTFLGS_DSZ64_DMR(dst, macro, src)

MOVEINSERTFLGS_DSZ64_DRR(dst, src0, src1)

group MOVEMERGEFLGS

Defines

MOVEMERGEFLGS_DSZ8_DRI(dst, src, imm)

MOVEMERGEFLGS_DSZ8_DIR(dst, imm, src)

MOVEMERGEFLGS_DSZ8_DRM(dst, src, macro)

MOVEMERGEFLGS_DSZ8_DMR(dst, macro, src)

MOVEMERGEFLGS_DSZ8_DRR(dst, src0, src1)

MOVEMERGEFLGS_DSZ16_DRI(dst, src, imm)

MOVEMERGEFLGS_DSZ16_DIR(dst, imm, src)

MOVEMERGEFLGS_DSZ16_DRM(dst, src, macro)

MOVEMERGEFLGS_DSZ16_DMR(dst, macro, src)

MOVEMERGEFLGS_DSZ16_DRR(dst, src0, src1)

MOVEMERGEFLGS_DSZ32_DRI(dst, src, imm)

MOVEMERGEFLGS_DSZ32_DIR(dst, imm, src)

MOVEMERGEFLGS_DSZ32_DRM(dst, src, macro)

MOVEMERGEFLGS_DSZ32_DMR(dst, macro, src)

MOVEMERGEFLGS_DSZ32_DRR(dst, src0, src1)

MOVEMERGEFLGS_DSZ64_DRI(dst, src, imm)

MOVEMERGEFLGS_DSZ64_DIR(dst, imm, src)

MOVEMERGEFLGS_DSZ64_DRM(dst, src, macro)

MOVEMERGEFLGS_DSZ64_DMR(dst, macro, src)

MOVEMERGEFLGS_DSZ64_DRR(dst, src0, src1)

group UJMPCC_DIRECT_NOTTAKEN

Defines

UJMPCC_DIRECT_NOTTAKEN_CONDO_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDO_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNO_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNO_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDB_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDB_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNB_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNB_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDZ_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDZ_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNZ_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNZ_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDBE_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDBE_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNBE_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNBE_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDS_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDS_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNS_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNS_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDP_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDP_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNP_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNP_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDL_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDL_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNL_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNL_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDLE_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDLE_RR(src0, src1)

UJMPCC_DIRECT_NOTTAKEN_CONDNLE_RI(src, imm)

UJMPCC_DIRECT_NOTTAKEN_CONDNLE_RR(src0, src1)

group MJMPCC_DSZNOP

Defines

MJMPCC_DSZNOP_CONDO_RI(src, imm)

MJMPCC_DSZNOP_CONDO_RR(src0, src1)

MJMPCC_DSZNOP_CONDNO_RI(src, imm)

MJMPCC_DSZNOP_CONDNO_RR(src0, src1)

MJMPCC_DSZNOP_CONDB_RI(src, imm)

MJMPCC_DSZNOP_CONDB_RR(src0, src1)

MJMPCC_DSZNOP_CONDNB_RI(src, imm)

MJMPCC_DSZNOP_CONDNB_RR(src0, src1)

MJMPCC_DSZNOP_CONDZ_RI(src, imm)

MJMPCC_DSZNOP_CONDZ_RR(src0, src1)

MJMPCC_DSZNOP_CONDNZ_RI(src, imm)

MJMPCC_DSZNOP_CONDNZ_RR(src0, src1)

MJMPCC_DSZNOP_CONDBE_RI(src, imm)

MJMPCC_DSZNOP_CONDBE_RR(src0, src1)

MJMPCC_DSZNOP_CONDNBE_RI(src, imm)

MJMPCC_DSZNOP_CONDNBE_RR(src0, src1)

MJMPCC_DSZNOP_CONDS_RI(src, imm)

MJMPCC_DSZNOP_CONDS_RR(src0, src1)

MJMPCC_DSZNOP_CONDNS_RI(src, imm)

MJMPCC_DSZNOP_CONDNS_RR(src0, src1)

MJMPCC_DSZNOP_CONDP_RI(src, imm)

MJMPCC_DSZNOP_CONDP_RR(src0, src1)

MJMPCC_DSZNOP_CONDNP_RI(src, imm)

MJMPCC_DSZNOP_CONDNP_RR(src0, src1)

MJMPCC_DSZNOP_CONDL_RI(src, imm)

MJMPCC_DSZNOP_CONDL_RR(src0, src1)

MJMPCC_DSZNOP_CONDNL_RI(src, imm)

MJMPCC_DSZNOP_CONDNL_RR(src0, src1)

MJMPCC_DSZNOP_CONDLE_RI(src, imm)

MJMPCC_DSZNOP_CONDLE_RR(src0, src1)

MJMPCC_DSZNOP_CONDNLE_RI(src, imm)

MJMPCC_DSZNOP_CONDNLE_RR(src0, src1)

group SETCC

Defines

SETCC_CONDO_DR(dst, src)

SETCC_CONDNO_DR(dst, src)

SETCC_CONDB_DR(dst, src)

SETCC_CONDNB_DR(dst, src)

SETCC_CONDZ_DR(dst, src)

SETCC_CONDNZ_DR(dst, src)

SETCC_CONDBE_DR(dst, src)

SETCC_CONDNBE_DR(dst, src)

SETCC_CONDS_DR(dst, src)

SETCC_CONDNS_DR(dst, src)

SETCC_CONDP_DR(dst, src)

SETCC_CONDNP_DR(dst, src)

SETCC_CONDL_DR(dst, src)

SETCC_CONDNL_DR(dst, src)

SETCC_CONDLE_DR(dst, src)

SETCC_CONDNLE_DR(dst, src)

group CMOVCC

Defines

CMOVCC_DSZ8_CONDO_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDO_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNO_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNO_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDB_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDB_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNB_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNB_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDZ_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDZ_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNZ_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNZ_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDBE_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDBE_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNBE_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNBE_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDS_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDS_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNS_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNS_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDP_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDP_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNP_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNP_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDL_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDL_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNL_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNL_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDLE_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDLE_DRR(dst, src0, src1)

CMOVCC_DSZ8_CONDNLE_DRI(dst, src, imm)

CMOVCC_DSZ8_CONDNLE_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDO_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDO_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNO_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNO_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDB_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDB_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNB_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNB_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDZ_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDZ_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNZ_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNZ_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDBE_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDBE_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNBE_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNBE_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDS_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDS_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNS_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNS_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDP_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDP_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNP_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNP_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDL_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDL_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNL_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNL_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDLE_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDLE_DRR(dst, src0, src1)

CMOVCC_DSZ16_CONDNLE_DRI(dst, src, imm)

CMOVCC_DSZ16_CONDNLE_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDO_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDO_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNO_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNO_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDB_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDB_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNB_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNB_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDZ_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDZ_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNZ_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNZ_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDBE_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDBE_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNBE_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNBE_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDS_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDS_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNS_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNS_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDP_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDP_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNP_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNP_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDL_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDL_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNL_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNL_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDLE_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDLE_DRR(dst, src0, src1)

CMOVCC_DSZ32_CONDNLE_DRI(dst, src, imm)

CMOVCC_DSZ32_CONDNLE_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDO_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDO_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNO_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNO_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDB_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDB_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNB_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNB_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDZ_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDZ_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNZ_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNZ_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDBE_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDBE_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNBE_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNBE_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDS_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDS_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNS_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNS_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDP_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDP_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNP_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNP_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDL_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDL_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNL_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNL_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDLE_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDLE_DRR(dst, src0, src1)

CMOVCC_DSZ64_CONDNLE_DRI(dst, src, imm)

CMOVCC_DSZ64_CONDNLE_DRR(dst, src0, src1)

group SELECTCC

Defines

SELECTCC_DSZ8_CONDO_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDO_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNO_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNO_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDB_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDB_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNB_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNB_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDZ_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDZ_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNZ_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNZ_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDBE_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDBE_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNBE_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNBE_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDS_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDS_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNS_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNS_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDP_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDP_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNP_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNP_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDL_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDL_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNL_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNL_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDLE_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDLE_DRR(dst, src0, src1)

SELECTCC_DSZ8_CONDNLE_DRI(dst, src, imm)

SELECTCC_DSZ8_CONDNLE_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDO_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDO_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNO_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNO_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDB_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDB_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNB_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNB_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDZ_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDZ_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNZ_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNZ_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDBE_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDBE_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNBE_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNBE_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDS_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDS_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNS_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNS_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDP_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDP_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNP_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNP_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDL_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDL_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNL_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNL_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDLE_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDLE_DRR(dst, src0, src1)

SELECTCC_DSZ16_CONDNLE_DRI(dst, src, imm)

SELECTCC_DSZ16_CONDNLE_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDO_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDO_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNO_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNO_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDB_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDB_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNB_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNB_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDZ_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDZ_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNZ_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNZ_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDBE_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDBE_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNBE_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNBE_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDS_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDS_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNS_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNS_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDP_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDP_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNP_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNP_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDL_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDL_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNL_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNL_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDLE_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDLE_DRR(dst, src0, src1)

SELECTCC_DSZ32_CONDNLE_DRI(dst, src, imm)

SELECTCC_DSZ32_CONDNLE_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDO_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDO_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNO_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNO_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDB_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDB_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNB_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNB_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDZ_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDZ_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNZ_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNZ_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDBE_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDBE_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNBE_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNBE_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDS_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDS_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNS_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNS_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDP_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDP_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNP_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNP_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDL_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDL_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNL_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNL_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDLE_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDLE_DRR(dst, src0, src1)

SELECTCC_DSZ64_CONDNLE_DRI(dst, src, imm)

SELECTCC_DSZ64_CONDNLE_DRR(dst, src0, src1)

group LDSTGBUF

Defines

LDSTGBUF_DSZ64_ASZ16_SC1_DI(dst, addr_imm)

LDSTGBUF_DSZ64_ASZ16_SC1_DR(dst, addr_reg)

group STADSTGBUF

Defines

STADSTGBUF_DSZ64_ASZ16_SC1_RI(src, addr_imm)

STADSTGBUF_DSZ64_ASZ16_SC1_RR(src, addr_reg)

group LDZX

For most cases, seg=0x0, mode=0x18 will work just fine.

Defines

LDZX_DSZ64_ASZ32_SC1_DR(dst, src, seg, mode)

LDZX_DSZ32_ASZ32_SC1_DR(dst, src, seg, mode)

LDZX_DSZ16_ASZ32_SC1_DR(dst, src, seg, mode)

LDZX_DSZ8_ASZ32_SC1_DR(dst, src, seg, mode)

LDZX_DSZN_ASZ32_SC1_DR(dst, src, seg, mode)

LDZX_DSZ64_ASZ32_SC1_DRR(dst, src0, src1, seg, mode)

LDZX_DSZ32_ASZ32_SC1_DRR(dst, src0, src1, seg, mode)

LDZX_DSZ16_ASZ32_SC1_DRR(dst, src0, src1, seg, mode)

LDZX_DSZ8_ASZ32_SC1_DRR(dst, src0, src1, seg, mode)

LDZX_DSZN_ASZ32_SC1_DRR(dst, src0, src1, seg, mode)

LDZX_DSZ64_ASZ32_SC1_DRI(dst, src, offset, seg, mode)

LDZX_DSZ32_ASZ32_SC1_DRI(dst, src, offset, seg, mode)

LDZX_DSZ16_ASZ32_SC1_DRI(dst, src, offset, seg, mode)

LDZX_DSZ8_ASZ32_SC1_DRI(dst, src, offset, seg, mode)

LDZX_DSZN_ASZ32_SC1_DRI(dst, src, offset, seg, mode)

LDZX_DSZ64_ASZ32_SC1_DRRI(dst, src0, src1, offset, seg, mode)

LDZX_DSZ32_ASZ32_SC1_DRRI(dst, src0, src1, offset, seg, mode)

LDZX_DSZ16_ASZ32_SC1_DRRI(dst, src0, src1, offset, seg, mode)

LDZX_DSZ8_ASZ32_SC1_DRRI(dst, src0, src1, offset, seg, mode)

LDZX_DSZN_ASZ32_SC1_DRRI(dst, src0, src1, offset, seg, mode)

group STAD

For most cases, seg=0x0, mode=0x18 will work just fine.

Defines

STAD_DSZ64_ASZ32_SC1_RR(src2, src, seg, mode)

STAD_DSZ32_ASZ32_SC1_RR(src2, src, seg, mode)

STAD_DSZ16_ASZ32_SC1_RR(src2, src, seg, mode)

STAD_DSZ8_ASZ32_SC1_RR(src2, src, seg, mode)

STAD_DSZN_ASZ32_SC1_RR(src2, src, seg, mode)

STAD_DSZ64_ASZ32_SC1_RRR(src2, src0, src1, seg, mode)

STAD_DSZ32_ASZ32_SC1_RRR(src2, src0, src1, seg, mode)

STAD_DSZ16_ASZ32_SC1_RRR(src2, src0, src1, seg, mode)

STAD_DSZ8_ASZ32_SC1_RRR(src2, src0, src1, seg, mode)

STAD_DSZN_ASZ32_SC1_RRR(src2, src0, src1, seg, mode)

STAD_DSZ64_ASZ32_SC1_RRI(src2, src, offset, seg, mode)

STAD_DSZ32_ASZ32_SC1_RRI(src2, src, offset, seg, mode)

STAD_DSZ16_ASZ32_SC1_RRI(src2, src, offset, seg, mode)

STAD_DSZ8_ASZ32_SC1_RRI(src2, src, offset, seg, mode)

STAD_DSZN_ASZ32_SC1_RRI(src2, src, offset, seg, mode)

STAD_DSZ64_ASZ32_SC1_RRRI(src2, src0, src1, offset, seg, mode)

STAD_DSZ32_ASZ32_SC1_RRRI(src2, src0, src1, offset, seg, mode)

STAD_DSZ16_ASZ32_SC1_RRRI(src2, src0, src1, offset, seg, mode)

STAD_DSZ8_ASZ32_SC1_RRRI(src2, src0, src1, offset, seg, mode)

STAD_DSZN_ASZ32_SC1_RRRI(src2, src0, src1, offset, seg, mode)

group SAVEUIP

Defines

SAVEUIP0_DI(dst, addr)

SAVEUIP1_DI(dst, addr)

SAVEUIP0_I(addr)

SAVEUIP1_I(addr)

group SAVEUIP_REGOVR

Defines

SAVEUIP_REGOVR0(imm)

SAVEUIP_REGOVR1(imm)

group READUIP_REGOVR

Defines

READUIP_REGOVR0(dst)

READUIP_REGOVR1(dst)

group URET

Defines

URET0

URET1

group UPDATEUSTATE

Defines

UPDATEUSTATE_I(testbits)

UPDATEUSTATE_NOT_I(testbits)

UPDATEUSTATE_RI(src, testbits)

UPDATEUSTATE_NOT_RI(src, testbits)

group TESTUSTATE

Defines

TESTUSTATE_UCODE(testbits)

TESTUSTATE_SYS(testbits)

TESTUSTATE_VMX(testbits)

TESTUSTATE_UCODE_NOT(testbits)

TESTUSTATE_SYS_NOT(testbits)

TESTUSTATE_VMX_NOT(testbits)

group UFLOWCTRL

Defines

FLOW_CTRL_UNK

FLOW_CTRL_URET0

FLOW_CTRL_URET1

FLOW_CTRL_LDAT_IN

FLOW_CTRL_MSLOOPCTR

FLOW_CTRL_USTATE

UFLOWCTRL_DR(dst, reg, uop)

UFLOWCTRL_R(reg, uop)

group AETTRACE

Defines

AETTRACE_DCR(dst, val, src)

AETTRACE_DCM(dst, val, macro)