uCode structure

Instruction

2431324344454647imm0opcodem1m2crc056111217182223src0src1dst/src2imm1m0
  • opcode
    A 12-bit opcode value. For some uops, additional information is encoded in the opcode.
    For example, in CMOVCC, DSZ and condition are encoded as below:
    012567891011CONDDSZCOND
  • src0/src1
    6-bit fields that specify which register to get input from.
    If the uppermost 3 bits equal 0b001, combine imm0, imm1, and src[0:2] to create a 16-bit immediate.
    If the uppermost 3 bits equal 0b010, combine imm0 and imm1 as an index into constants ROM.
  • dst/src2
    6-bit field that specifies register to send the output of the operation to.
    For some memory-related uops, used as a src register instead.
  • imm0/imm1
    In most uops, used as a 16-bit immediate value in src as specified above.
    In some uops, e.g. in memory operations, imm0 and imm1 are used as two separate immediates by the instruction.
  • m0/m1/m2
    Several bits that change the mode of uops.
    For most operations, m0 means that the immediate value should be interpreted as a macro immediate.
    For TESTUSTATE/UPDATEUSTATE m0 is used to invert the operation.
  • crc

    2-bit crc. The first bit is the xor of all even-indexed bits. The second bit is the xor of all odd-indexed bits.

Sequence Word

012567822232425272829up0eflowup1uaddrup2synccrc
  • up0/up1/up2

    2-bit pointers to uop in triad to perform operation on. See operations below. For up1 and up2, the value 3 specifies NOP

  • 0 eflow
    A 4-bit enum which specifies which eflow operation to run.
    The operation is run after the uop pointed to by up0 has been run.

      1. NOP

      1. URET0

      1. URET1

      1. SAVEUIP0

      1. SAVEUIP1

      1. SAVEUIP0_REGOVR

      1. SAVEUIP1_REGOVR

      1. WRTAGW

      1. MSLOOP

      1. MSSTOP

      1. UEND0

      1. UEND1

      1. UEND2

      1. UEND3

  • 1 uaddr
    Address to jump to after uop pointed to by up1 has been run. If up1=3, this is ignored.
    This is always run after eflow if up0=up1.
    This is turned into a conditional jump if preceded by TESTUSTATE or SUBR.
  • 2 sync
    A 3-bit enum that specifies synchronization of the operation. For example load fences and synchronization barriers.
    Synchronization is performed on the uop pointed by up2 and ignored if up2=3.

      1. LFNCEWAIT

      1. LFNCEMARK

      1. LFNCEWTMRK

      1. SYNCFULL

      1. SYNCWAIT

      1. SYNCMARK

      1. SYNCWTMRK

  • crc

    2-bit crc. The first bit is the xor of all even-indexed bits. The second bit is the xor of all odd-indexed bits.